Exploring STM32WBA6xx Memory Protection Architecture

Deep dive into OTP memory, write-protection, and option bytes

Key Insights

Protected Memory Organization: The STM32WBA6xx series features a sophisticated memory protection setup with configurable regions using option bytes and an MPU.
OTP Memory Characteristics: OTP memory is available, organized in blocks with a fixed size, with the ability to program repeatedly until lock-in.
Flash Write Protection & Option Bytes: Write-protected flash regions are determined by option bytes, and a defined process ensures secure updating and locking of protected memory.

1. Protected Memory Organization

The STM32WBA6xx series of microcontrollers incorporates a detailed memory protection strategy. This organization leverages several mechanisms:

Memory Protection Unit (MPU)

The MPU allows the system to divide memory into different regions with specific permissions to prevent unauthorized access or modification. This is critical for ensuring that sensitive sections of memory are secured during software execution.

Write-Protected Flash Memory

Write-protected flash memory is implemented using option bytes, which define the start and end pages for a protection range. Depending on the setup, several blocks (often in multiples such as up to 16 areas in many STM32 architectures) can be defined, though the precise number of flash protection blocks is determined by the internal flash controller's configuration. Each block is sized based on the flash's page granularity, which might be, for example, a single sector (ranging from 16K to 128K) or a part of the flash array. The option bytes control these ranges, and altering them involves a specific update process.

2. One-Time Programmable (OTP) Memory

In addition to flash memory, the STM32WBA6xx series provides one-time programmable (OTP) memory designed for storing small amounts of critical non-volatile data such as unique IDs or calibration constants.

Availability and Organized Size

OTP memory is indeed available in the STM32WBA6xx series. Documented details from multiple sources indicate variances in OTP organization. One approach shows it divided into blocks; for instance, one reference indicates there are 16 blocks of 32 bytes each (totaling 512 bytes), while other documentation suggests a possible configuration up to 16 Kbytes in some models. The most common and reliable information from detailed integration points (particularly answer C) indicates 16 blocks of 32 bytes comprise the OTP, which sums up to 512 bytes.

Programming Behavior and Block Locking

Before a block is permanently locked to become non-rewritable, it can be written to multiple times. This allows you to verify and update data until you decide the block should be immutable. Once the decision is made, locking the block (by programming a specific lock indicator) renders that block permanently non-writable.

Smallest Lockable Block

The smallest block that can be made non-rewritable is typically the size of a single OTP block, which in the common implementation is 32 bytes. In some other series the smallest programmable unit might vary (ranging from a double word to 32 bytes), but for the STM32WBA6xx series, the consensus among technical sources is that it is 32 bytes.

3. Write-Protected Flash Memory

Write-protected flash memory regions are defined using the option bytes, which segment the flash memory into multiple areas to restrict write access.

Defining Multiple Blocks

The number of write-protected blocks is not strictly limited by a fixed number in the underlying architecture. The STM32WBA6xx series can define multiple protection regions using the option bytes, with several sources noting that up to 16 regions might be possible. The actual number depends on the flash memory controller design and available page-based granularity.

Size Limitations of Each Protected Region

Each protected region’s size is governed by the flash page size, meaning that you can only lock sections that conform to this granularity. There is no arbitrary size limit besides these page boundaries; therefore, a region might be a single page or multiple contiguous pages—depending on the application needs.

4. Process for Setting/Updating Option Bytes

Option bytes play a crucial role in configuring memory protection for both flash and OTP memory. They are pre-configured settings that load automatically on power-up, and they require a specific programming sequence to update.

Step-by-Step Process

Unlock Access: Begin by unlocking the FLASH control register (FLASH_CR), typically using a specific key unlocking algorithm. This involves sending a LOCK clearing sequence to allow modifications.
Option Key Programming: Write the two key values (often named OPTKEY1 and OPTKEY2) into the FLASH option key register to enable option byte programming.
Set/Update Option Bytes: Once unlocked, modify the specific option bytes responsible for defining write protection start and end pages, readout protection, and other security configurations. In the case of OTP memory, program the corresponding data into OTP regions.
Validate Programming: Option bytes are typically verified through complementary words to ensure data integrity.
Lock the Registers: After the programming sequence, re-lock the FLASH option registers to prevent accidental modifications. The changes will take effect immediately upon power cycle or by toggling the OBL_LAUNCH bit.

This sequential process ensures that memory protection settings are securely updated without risking inadvertent modifications that could lead to system vulnerabilities.

Visual Data Representations

Radar Chart: Security & Protection Scores

Below is a visual representation of the qualitative assessment scores for various aspects of the memory protection features in the STM32WBA6xx microcontrollers.

Mermaid Mindmap: STM32WBA6xx Memory Protection Overview

The mermaid diagram below provides a mindmap overview of the memory protection architecture, organized by OTP memory, flash write protection, and option byte management.

graph TD A["STM32WBA6xx Memory Protection"] --> B[MPU Configuration] A --> C[OTP Memory] A --> D[Flash Write Protection] A --> E[Option Bytes Process] C --> F["Available OTP (512 bytes)"] C --> G["32-byte Block Locking"] D --> H["Multiple Blocks (up to 16)"] D --> I["Page Granularity"] E --> J["Unlock FLASH_CR"] E --> K["Program OPTKEY1/OPTKEY2"] E --> L["Set/Verify Option Bytes"] E --> M["Lock Registers and Reset"]

Summary Table: Key Memory Protection Parameters

The table below summarizes the critical parameters of the memory protection features for the STM32WBA6xx series.

Feature	Description	Parameter/Value
Protected Regions	Division of internal memory via MPU and option bytes	Multiple configurable regions (up to 16+)
OTP Memory Availability	Non-volatile memory available for calibration and unique data	Commonly 512 bytes (16 blocks x 32 bytes)
OTP Write Behavior	Writable repeatedly until locked, then permanently non-writable	Yes, until block lock
Smallest OTP Block	Smallest granularity limited by design	32 bytes per block
Flash Write Protection Blocks	Defined through option bytes based on flash page size	Typically up to 16 regions, size-bound by flash page
Option Bytes Programming	Sequential unlocking, updating, verifying and locking process	Unlock FLASH_CR, program keys, set bytes, validate, re-lock

Frequently Asked Questions (FAQ)

How is the memory protection structured in STM32WBA6xx MCUs?

The STM32WBA6xx family organizes its memory into configurable regions using a Memory Protection Unit (MPU), with additional write-protection for flash and one-time programmable (OTP) memory segments defined via option bytes.

Is OTP memory available, and what is its capacity?

Yes, OTP memory is available. Common implementations indicate 512 bytes of OTP memory, organized into 16 blocks of 32 bytes each.

What is the process for updating the option bytes for memory protection?

The process involves unlocking the flash control registers, writing specific option keys (such as OPTKEY1 and OPTKEY2), updating the desired option bytes to configure protected regions, verifying these settings, and finally re-locking the registers to enforce the changes.